Advanced Packaging Products – At a Glance

Advanced packaging product involves a standard grouping of various distinctive techniques such as 2.5D, fan-out wafer-level package, system-in-package, and 3D-IC.

Conventional industries depended upon the innovative architectures and conventional chips scaling for a new device. In the case of chip scaling, the notion was to pack additional transistors on a system-on-a-chip or a Monolithic die at every process node. This enabled a faster chip at a lower cost for each transistor. However, the traditional chip scaling was becoming more expensive and difficult at every node.

The driving force for Advanced Packaging Solutions & Products Inc. is positively correlated with the popular Moore’s Law. The wires and transistors shrink, and the length of distance that signals require to travel or to transmit from one part of a chip to another over thin wires increases at every node. These chips are connected together by using thicker pipes that are available in the form of interposers, through-silicon vias, simple wires, or bridges. The signal’s speed can be raised and the energy amount needed to drive the signals can be diminished. Moreover, based on the type of package, there can be lesser physical effects and the components that are produced at different nodes can be combined.

Advanced packaging approaches are being used for wide-ranging products. However, the initial concern about time and cost continues to slow down the process of adoption. EDA firms have developed new tools that automate the process of advanced packaging and OSATs are continually refining these processes, making it less expensive and more predictable.

There are various methods by which a chip design can be implemented using heterogeneous integration. The issue with advanced packaging products is the cost factor since the technology still remains really expensive for various niche applications. The companies mentioned below have introduced new packaging technologies which are most likely to address this problem of high cost and also other challenges in this field –

  • ASE has described high-density fan-out technology which supports HBM or high bandwidth memory.
  • Leti and STMicroelectronics jointly have described the 3D packaging technology by using chiplets. The idea of using chiplets involved a list of modular chips in the library. These chiplets can be integrated into a package by using a die-to-die interconnection scheme.
  • TSMC has described details about the next generation 3D Technology and fan-out Technology.

Flip-chip and Wirebond

There was a time when IC packaging was not popular in the industry of semiconductor. The packaging was simple and the cost of packaging was the lowest. However, the advancements enabled chips to have the smaller form factor and this paved their way to an advanced form of heterogeneous integration. If one wants high-performance, he will require different packages that have more I/Os. Worth mentioning there is no single full package that meets all the requirements of both markets.

There is another way by which one can segment the market of packaging and that is by the interconnect type. This includes flip-chip, wire-bond, wafer-level packaging, and TVS or through-silicon vias.

Wire bonder stitches 1 chip to another or substrate by using small wires. The wire bonding process is used in low-cost legacy packaging, memory dies stacking, and mid-range packages.

For processors, however, the wirebond does not offer enough I/Os. Hence, a flip-chip is more superior than a wire bond when it comes to increasing that number. Fan-out on the other hand is in between the two in terms of the I/Os whereas, the 2.5D and 3D are at a far superior end.

Fan-out, Chiplets, 2.5D/3D

Just after the flip-chip, the next that came in the I/O hierarchy was the fan-out. It has recently gained a lot of attention after Apple started using info fan-out packages of TSMC for their iPhones. The package integrates the application processor of Apple and the third-party memory of the same unit. This enables more I/Os compared to other types of packages.

Fan-out does not need an interposer which is why it is much cheaper compared to the 2.5D and 3D technologies. The packaging of the dies is done on a wafer and hence it is known as a wafer-level package. It is split into 2 segments namely, low and high density. The low-density fan-out is used mainly for power management and the high-density fan-out is used for smartphones and servers.

One of the major culprits is the DRAM, the data rates of which seem to have been lacking, especially in the requirements of memory bandwidth. The solution to this problem is HBM or high-bandwidth memory which loads DRAM dies one above the other and connects it with the TSVs. This enables more bandwidth and I/Os.

Generally, the HBM is added in the 2.5D package where the dies are placed of stacked side-by-side on an interposer. The interposer behaves like a bridge between the board and the chips.

Typically, the 2.5D or 3D is very costly the HBM relegated for most of the high-end applications. Moreover, the fan-out packaging with HBM has more advantages over the 2.5D and 3D such as the electrical performance in fan-out which is far superior to the latter.

When it comes to chiplets, there are some challenges too, faced by the industry. The packaging is implemented most commonly in the high-end applications and that has generally brought down the costs.

Integrating the chiplets into the package is not an easy task. The lithography challenges increase as more individual chiplets are used in completing one single package. This leads to interconnect overlays and involves the process of TSV for chip interconnect and the productivity or system throughput which provides the required technical solution at a cheaper cost.

For a heterogeneous integration, the requirements of quality for the devices being integrated are rising rapidly. The requirements are demanding for a more accurate die screening, the value of and the number of ICs put together into a system-in-package is also increasing. For die-level and wafer-level, the subtle or small defects that were previously acceptable have now become unacceptable with the incorporation of the dies in complicated, multi-device packages. The whole heterogenous package can be ruined with just 1 die in the system-in-package.